Quartus Verilog HDL/FPGA 双精度64位IEEE754浮点数比大小模块:大于,小于,等于,不等于
module double_decode( //解码double(双精度浮点数)的符号位,指数位,尾数位
input double, // 双精度浮点数输入
output sign, //符号位 0:正数 1:负数
output nan, //NAN非数字标志位 指数位最大且尾数位不为0
output signed exponent, // 指数位 范围:-1023~1024
output fraction // 尾数位 范围:0~4503599627370495
);
assign sign = (|double) ? double : 1'b0; //负0转正0
assign exponent = double - 11'd1023;
assign fraction = double;
assign nan = (&double && |fraction);
endmodule
module double_cmp( //64位双精度浮点数 比较两个数值的大小
input ain, // 被比较数A
input bin, // 比较数B
output reg equ, //A等于B (NAN只能等于或不等于比较)
output neq, //A不等于B (NAN不比较符号位)
output lss, //A小于B (A小于B输出1,否则0)
output leq, //A小于等于B
output reg gtr, //A大于B
output geq //A大于等于B
);
wire signA;
wire signed exponentA;
wire fractionA;
wire nanA;
double_decode A(
.double(ain),
.sign(signA),
.nan(nanA),
.exponent(exponentA),
.fraction(fractionA)
);
wire signB;
wire signed exponentB;
wire fractionB;
wire nanB;
double_decode B(
.double(bin),
.sign(signB),
.nan(nanB),
.exponent(exponentB),
.fraction(fractionB)
);
wire nan = |{nanA,nanB};
assign neq = !equ;
assign geq = nan ? 1'b0 : |{gtr,equ};
assign lss = nan ? 1'b0 : !geq;
assign leq = nan ? 1'b0 : !gtr;
always @(*) begin
equ = 1'b0;
if(ain == 63'd0 && bin == 63'd0) begin //正负零不比较符号位
equ = 1'b1;
end else if(ain == bin || (nanA && nanB)) begin
equ = 1'b1;
end
end
always @(*) begin
gtr = 1'b0;
if(!nan) begin
if(signA != signB) begin //符号位不同
gtr = signB;
end else begin //符号位相同
if(exponentA > exponentB) begin //A指数大于B指数
gtr = !signB;
end else if(exponentA < exponentB) begin //A指数小于B指数
gtr = signB;
end else begin //A与B指数相同,比较尾数
gtr = signB ? (fractionA < fractionB) : (fractionA > fractionB);
end
end
end
end
endmodule
module main(
input ain,
input bin,
output equ,
output neq,
output lss,
output leq,
output gtr,
output geq
);
double_cmp double_cmp(
.ain(ain),
.bin(bin),
.equ(equ),
.neq(neq),
.lss(lss),
.leq(leq),
.gtr(gtr),
.geq(geq)
);
endmodule
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