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- module clk_div( //时钟分频模块
- input clk, //时钟输入
- output clk_d2, //时钟2分频
- output clk_d4, //时钟4分频
- output clk_d8, //时钟8分频
- output clk_d16, //时钟16分频
- output clk_d32, //时钟32分频
- output clk_d64, //时钟64分频
- output clk_d128, //时钟128分频
- output clk_d256 //时钟256分频
- );
- reg [7:0] i;
- assign {
- clk_d256,
- clk_d128,
- clk_d64,
- clk_d32,
- clk_d16,
- clk_d8,
- clk_d4,
- clk_d2
- } = i;
- always @(posedge clk) begin
- i <= i + 1'd1;
- end
- endmodule
- module main(
- input clk, //50Mhz Pin17
- output reg led //LED Pin3
- );
- clk_div u1( //模块实例化
- .clk(clk), //50Mhz
- .clk_d2(), //25Mhz
- .clk_d4(), //12.5Mhz
- .clk_d8(), //6.25Mhz
- .clk_d16(), //3.125Mhz
- .clk_d32(), //1.5625Mhz
- .clk_d64(clkB), //781.25Khz
- .clk_d128(), //390.625Khz
- .clk_d256(), //195.3125Khz
- );
- wire clkB;
- integer i = 0;
- always @(posedge clkB) begin
- i = i + 1'd1;
- if(i >= 390625) begin
- i = 0;
- led <= !led;
- end
- end
- endmodule
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