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本帖最后由 HDL 于 2022-12-8 06:25 编辑
- module main(
- input clk, //50Mhz有源晶振 Pin17
- input key, //轻触开关 按键(低电平按下) Pin144 (按Ctrl+Shift+A将该口配置为上拉电阻模式)
- //3个共阳LED
- output led1, //LED1(低电平点亮) Pin3
- output led2, //LED2 Pin7
- output led3 //LED3 Pin9
- );
- reg [2:0] i;
- assign {led3,led2,led1} = ~i;
- integer j,k;
- wire skey = (k >= 1250000) ? 1'b1 : 1'b0; //消抖1250000个时钟(25ms)
- always @(posedge clk) begin //50Mhz时钟上升沿
- if(key) begin //按键松开
- k <= 0; //计数清0
- end else begin //按键按下
- if(!(&k)) begin //计数未加满
- k <= k + 1; //计数+1
- end
- end
- end
- always @(posedge clk) begin
- if(skey) begin //按键按下 (已消抖)
- i <= 3'd0; //LED熄灭
- j <= 0; //计数清0
- end else begin
- j = j + 1; //计数+1
- if(j >= 12500000) begin //此值越小,LED闪烁速度越快
- j = 0;
- i <= i + 3'd1; //LED二进制累加
- end
- end
- end
- endmodule
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