Quartus Verilog HDL/FPGA 组合逻辑模块实例化实现判断一个11位手机号码格式是否有效

发表于 2023-3-10 18:27:05 | 显示全部楼层 |阅读模式

module is_cell_phone_number( //手机号格式判断模块
input [34:0] number, //35位宽 11位手机号范围:13000000000~19999999999
output ok //有效输出1 无效输出0
);
assign ok = (number >= 35'd13000000000 && number <= 35'd19999999999) ? 1'd1 : 1'd0;
endmodule
module main(
input clk, //时钟输入
output reg led //低电平(计算正确)点亮
);
wire ok;
is_cell_phone_number U1(
.number(35'd18888888888),
.ok(ok)
);
always @(posedge clk) begin
led <= !ok;
end
endmodule

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