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- module digital_tube( //3位共阴数码管驱动模块
- input clk, //50Mhz时钟
- input [7:0] A, //百位段码
- input [7:0] B, //十位段码
- input [7:0] C, //个位段码
- output reg [7:0] sc, //8位宽数码管段码 [0]:A [1]:B ... [6]:G [7]:DP
- output reg [2:0] bc //3位宽数码管位码 [0]:百位 [1]:十位 [2]:个位
- );
- reg [15:0] i;
- reg [1:0] j;
- reg [23:0] k;
- always @(posedge clk) begin
- i = i + 16'd1;
- if(i >= 16'd50000) begin //50000个时钟即为1ms
- i = 0;
- if(j == 0) begin
- k = {A,B,C};
- end
- case(j)
- 2'd0:sc <= k[23:16];
- 2'd1:sc <= k[15:8];
- 2'd2:sc <= k[7:0];
- default:sc <= 8'd0;
- endcase
- bc <= ~(1'd1 << j);
- j = j + 2'd1;
- if(j == 3) begin
- j = 0;
- end
- end
- end
- endmodule
- module max6675( //MAX6675 K型热电偶芯片驱动模块
- input CLK, //时钟输入 390.625Khz
- input SO, //MAX6675 数据
- output reg SCK, //MAX6675 时钟
- output reg CS, //MAX6675 片选
- output reg [15:0] out //从MAX6675 读取到的16位宽数据
- /*
- [15]:伪符号位 (固定为0,1为芯片通信异常)
- [14:3]:12位温度摄氏度(精度0.25度)
- [2]:0:热电偶已连接,1:断开
- [1]:标识符 [0]:三态
- */
- );
- integer delay_clk; //延时时钟
- reg [15:0] dat;
- reg [4:0] order;
- always @(posedge CLK) begin
- if(delay_clk != 0) begin
- delay_clk <= delay_clk - 1;
- CS <= 1'd1;
- SCK <= 1'd0;
- end else begin
- order <= order + 5'd1;
- case(order)
- 5'd0:CS <= 1'b0; //CS拉低
- 5'd1:{dat[15],SCK} <= {SO,1'd1}; //采集SO数据并将SCK拉高
- 5'd2:SCK <= 1'd0; //SCK拉低瞬间SO发生改变
- 5'd3:{dat[14],SCK} <= {SO,1'd1};
- 5'd4:SCK <= 1'd0;
- 5'd5:{dat[13],SCK} <= {SO,1'd1};
- 5'd6:SCK <= 1'd0;
- 5'd7:{dat[12],SCK} <= {SO,1'd1};
- 5'd8:SCK <= 1'd0;
- 5'd9:{dat[11],SCK} <= {SO,1'd1};
- 5'd10:SCK <= 1'd0;
- 5'd11:{dat[10],SCK} <= {SO,1'd1};
- 5'd12:SCK <= 1'd0;
- 5'd13:{dat[9],SCK} <= {SO,1'd1};
- 5'd14:SCK <= 1'd0;
- 5'd15:{dat[8],SCK} <= {SO,1'd1};
- 5'd16:SCK <= 1'd0;
- 5'd17:{dat[7],SCK} <= {SO,1'd1};
- 5'd18:SCK <= 1'd0;
- 5'd19:{dat[6],SCK} <= {SO,1'd1};
- 5'd20:SCK <= 1'd0;
- 5'd21:{dat[5],SCK} <= {SO,1'd1};
- 5'd22:SCK <= 1'd0;
- 5'd23:{dat[4],SCK} <= {SO,1'd1};
- 5'd24:SCK <= 1'd0;
- 5'd25:{dat[3],SCK} <= {SO,1'd1};
- 5'd26:SCK <= 1'd0;
- 5'd27:{dat[2],SCK} <= {SO,1'd1};
- 5'd28:SCK <= 1'd0;
- 5'd29:{dat[1],SCK} <= {SO,1'd1};
- 5'd30:SCK <= 1'd0;
- default:begin
- {dat[0],SCK} = {SO,1'd1};
- out = dat;
- delay_clk <= 390625; //延时1秒
- end
- endcase
-
- end
- end
- endmodule
- module main(
- input clk, //50Mhz Pin17
- input so, //MAX6675 Pin40
- output sck, //MAX6675 Pin42
- output [7:0] test, //接8通道逻辑分析仪 Pin:41,43,45,48,52,55,58,60
- output cs, //MAX6675 Pin44
- //接3位共阴数码管
- output [7:0] sc, //8位宽 数码管段码
- output [2:0] bc //3位宽 数码管位码
- );
- function [7:0] display; //16进制数码管段码查询
- input [3:0] hex;
- begin
- case(hex)
- 4'h0:display = 8'h3F;
- 4'h1:display = 8'h06;
- 4'h2:display = 8'h5B;
- 4'h3:display = 8'h4F;
- 4'h4:display = 8'h66;
- 4'h5:display = 8'h6D;
- 4'h6:display = 8'h7D;
- 4'h7:display = 8'h07;
- 4'h8:display = 8'h7F;
- 4'h9:display = 8'h6F;
- 4'hA:display = 8'h77;
- 4'hB:display = 8'h7C;
- 4'hC:display = 8'h39;
- 4'hD:display = 8'h5E;
- 4'hE:display = 8'h79;
- 4'hF:display = 8'h71;
- endcase
- end
- endfunction
- reg [6:0] i; //时钟分频 [0]:25M [1]:12.5M [2]:6.25M [3]:3.125M [4]:1.5625M [5]:781.25K [6]:390.625K
- wire clkb = i[6];
- always @(posedge clk) begin
- i <= i + 7'd1;
- end
- wire [15:0] max6675_data;
- wire chip = !max6675_data[15]; //MAX6675芯片连接标志 (1:已连接 0:未连接)
- wire link = !max6675_data[2]; //热电偶连接标志 (1:已连接 0:未连接)
- assign test[0] = clkb;
- assign test[1] = so;
- assign test[2] = sck;
- assign test[3] = cs;
- assign test[4] = 1'd1;
- assign test[5] = 1'd0;
- assign test[6] = 1'd1;
- assign test[7] = 1'd0;
- wire [9:0] a = max6675_data[14:5];
- wire [9:0] temp = (a > 999) ? 10'd999 : a; //测量摄氏度 精度1度 最大999度
- max6675 max6675(
- .CLK(clkb),
- .SO(so),
- .SCK(sck),
- .CS(cs),
- .out(max6675_data)
- );
- //小数点亮:MAX6675初始化异常 3个减号:热电偶接触不良
- digital_tube digital_tube(
- .clk(clk),
- .A(chip ? (link ? display(temp/100%10) : 8'h40) : 8'h80),
- .B(chip ? (link ? display(temp/10%10) : 8'h40) : 8'h80),
- .C(chip ? (link ? display(temp%10) : 8'h40) : 8'h80),
- .sc(sc),
- .bc(bc)
- );
- endmodule
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