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Quartus Verilog HDL/FPGA 将7位宽10进制数字:0~99 转换到 8位宽16进制数字:0x00~0x99

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发表于 2023-4-19 09:55:46 | 显示全部楼层 |阅读模式
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  1. module main(                        //将10进制数字:0~99 转换成16进制数字:0x00~0x99
  2.         input [6:0] d,                //[7位宽] 输入10进制:26 输出16进制:0x26 以此类推
  3.         output [7:0] h                //[8位宽] 输入若大于99,输出:0xFF
  4. );

  5. //以下两行除法与求余运算需占用98个逻辑:
  6. //wire [3:0] s = (d >= 100) ? 4'hF : d/7'd10;
  7. //wire [3:0] g = (d >= 100) ? 4'hF : d%7'd10;


  8. //以下代码仅占用43个逻辑:
  9. reg [3:0] s;        //十位
  10. reg [3:0] g;        //个位

  11. always @(*) begin
  12.         {s,g} = 8'd0;
  13.         //十位
  14.         if(d >= 10) s = 4'd1;
  15.         if(d >= 20) s = 4'd2;
  16.         if(d >= 30) s = 4'd3;
  17.         if(d >= 40) s = 4'd4;
  18.         if(d >= 50) s = 4'd5;
  19.         if(d >= 60) s = 4'd6;
  20.         if(d >= 70) s = 4'd7;
  21.         if(d >= 80) s = 4'd8;
  22.         if(d >= 90) s = 4'd9;
  23.         //个位
  24.         if(d == 1 || d == 11 || d == 21 || d == 31 || d == 41 || d == 51 || d == 61 || d == 71 || d == 81 || d == 91) g = 4'd1;
  25.         if(d == 2 || d == 12 || d == 22 || d == 32 || d == 42 || d == 52 || d == 62 || d == 72 || d == 82 || d == 92) g = 4'd2;
  26.         if(d == 3 || d == 13 || d == 23 || d == 33 || d == 43 || d == 53 || d == 63 || d == 73 || d == 83 || d == 93) g = 4'd3;
  27.         if(d == 4 || d == 14 || d == 24 || d == 34 || d == 44 || d == 54 || d == 64 || d == 74 || d == 84 || d == 94) g = 4'd4;
  28.         if(d == 5 || d == 15 || d == 25 || d == 35 || d == 45 || d == 55 || d == 65 || d == 75 || d == 85 || d == 95) g = 4'd5;
  29.         if(d == 6 || d == 16 || d == 26 || d == 36 || d == 46 || d == 56 || d == 66 || d == 76 || d == 86 || d == 96) g = 4'd6;
  30.         if(d == 7 || d == 17 || d == 27 || d == 37 || d == 47 || d == 57 || d == 67 || d == 77 || d == 87 || d == 97) g = 4'd7;
  31.         if(d == 8 || d == 18 || d == 28 || d == 38 || d == 48 || d == 58 || d == 68 || d == 78 || d == 88 || d == 98) g = 4'd8;
  32.         if(d == 9 || d == 19 || d == 29 || d == 39 || d == 49 || d == 59 || d == 69 || d == 79 || d == 89 || d == 99) g = 4'd9;
  33.         if(d >= 100) {s,g} = 8'hFF;
  34. end
  35. assign h = {s,g};
  36. endmodule
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