|
- module hc09( //集电极(漏极)开路的四组二输入与门 VCC:Pin14 GND:Pin7
- //1组
- input A1, //与门输入A Pin1
- input B1, //与门输入B Pin2
- output Y1, //与门输出Y Pin3
- //2组
- input A2, //Pin4
- input B2, //Pin5
- output Y2, //Pin6
- //3组
- input A3, //Pin9
- input B3, //Pin10
- output Y3, //Pin8
- //4组
- input A4, //Pin12
- input B4, //Pin13
- output Y4 //Pin11
- );
- assign {Y1,Y2,Y3,Y4} = {
- (A1 & B1) ? 1'bz : 1'b0,
- (A2 & B2) ? 1'bz : 1'b0,
- (A3 & B3) ? 1'bz : 1'b0,
- (A4 & B4) ? 1'bz : 1'b0
- };
- endmodule
- module main(
- input clk,
- output reg led //低电平(计算正确)点亮
- );
- wire Y;
- hc09 U1(
- .A1(1'b0),
- .B1(1'b0),
- .Y1(Y),
- .A2(1'b0),
- .B2(1'b1),
- .Y2(Y),
- .A3(1'b1),
- .B3(1'b0),
- .Y3(Y),
- .A4(1'b0),
- .B4(1'b0),
- .Y4(Y)
- );
- always @(posedge clk) begin
- if(Y == 0) begin
- led <= 1'b0;
- end else begin
- led <= 1'b1;
- end
- end
- endmodule
复制代码 |
|