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- module hc135( //二组五进二出异或门 同或门 异或非门 VCC:Pin16 GND:Pin8
- //A组
- input A1A, //输入A1 Pin1
- input B1A, //输入B1 Pin2
- input CA, //输入C 低电平:异或 高电平:同或 Pin4
- input A2A, //输入A2 Pin5
- input B2A, //输入B2 Pin6
- output Y1A, //输出Y1 Pin3
- output Y2A, //输出Y2 Pin7
- //B组
- input A1B, //输入A1 Pin10
- input B1B, //输入B1 Pin11
- input CB, //输入C 低电平:异或 高电平:同或 Pin12
- input A2B, //输入A2 Pin14
- input B2B, //输入B2 Pin15
- output Y1B, //输出Y1 Pin9
- output Y2B //输出Y2 Pin13
- );
- assign Y1A = ^{A1A,B1A,CA};
- assign Y2A = ^{A2A,B2A,CA};
- assign Y1B = ^{A1B,B1B,CB};
- assign Y2B = ^{A2B,B2B,CB};
- endmodule
- module main(
- input clk, //时钟输入
- output reg led //低电平(计算正确)点亮
- );
- reg [9:0] in = 10'd0;
- wire [3:0] out;
- hc135 U1(
- .A1A(in[9]),
- .B1A(in[8]),
- .CA(in[7]),
- .A2A(in[6]),
- .B2A(in[5]),
- .Y1A(out[3]),
- .Y2A(out[2]),
- .A1B(in[4]),
- .B1B(in[3]),
- .CB(in[2]),
- .A2B(in[1]),
- .B2B(in[0]),
- .Y1B(out[1]),
- .Y2B(out[0])
- );
- always @(posedge clk) begin
- in <= in + 10'd1;
- if(out[3] == ^in[9:7] && out[2] == ^in[7:5] && out[1] == ^in[4:2] && out[0] == ^in[2:0]) begin
- led <= 1'b0;
- end else begin
- led <= 1'b1;
- end
- end
- endmodule
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