Quartus Verilog HDL/FPGA 实现 CD4026/74HC4026 7段共阴数码管显示的10进制计数器

HDL · 发表于 2023-11-22 10:05:43

module cd4026( //7段共阴数码管显示的10进制计数器 VCC:Pin16 GND:Pin8
input CLK, //计数时钟(上升沿触发) Pin1
input INH, //低电平使能CLK信号高电平禁止 Pin2
input DEI, //高电平打开显示低电平关闭 (不影响计数) Pin3
input MR, //异步上升沿计数清零 Pin15
//静态共阴数码管段码A~G
output A, //Pin10
output B, //Pin12
output C, //Pin13
output D, //Pin9
output E, //Pin11
output F, //Pin6
output G, //Pin7
output CO, //计数为9输出低电平,否则高电平接下片的CLK Pin5
output DEO, //DEO直通DEI 接下一片的DEI Pin4
output UCS //计数为2输出低电平否则高电平 Pin14
);
reg [3:0] count = 4'd0; //计数寄存器范围:0~9
function [6:0] display; //10进制7段共阴数码管段码查询
input [3:0] dec; //[4位宽]10进制数字范围:0~9
begin
case(dec)
4'd0:display = 7'h3F;
4'd1:display = 7'h06;
4'd2:display = 7'h5B;
4'd3:display = 7'h4F;
4'd4:display = 7'h66;
4'd5:display = 7'h6D;
4'd6:display = 7'h7D;
4'd7:display = 7'h07;
4'd8:display = 7'h7F;
4'd9:display = 7'h6F;
default:display = 7'h00;
endcase
end
endfunction
assign {G,F,E,D,C,B,A} = DEI ? display(count) : 7'd0;
assign CO = (count != 4'd9);
assign DEO = DEI;
assign UCS = (count != 4'd2);
always @(posedge CLK or posedge MR) begin
if(MR) begin
count <= 4'd0;
end else if(CLK && !INH) begin
if(count >= 4'd9) begin
count <= 4'd0;
end else begin
count <= count + 4'd1;
end
end
end
endmodule
module main(
input CLK,
input INH,
input DEI,
input MR,
output A,
output B,
output C,
output D,
output E,
output F,
output G,
output CO,
output DEO,
output UCS
);
cd4026 U1(
.CLK(CLK),
.INH(INH),
.DEI(DEI),
.MR(MR),
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.F(F),
.G(G),
.CO(CO),
.DEO(DEO),
.UCS(UCS)
);
endmodule

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Quartus Verilog HDL/FPGA 实现 CD4026/74HC4026 7段共阴数码管显示的10进制计数器

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