Quartus Verilog HDL/FPGA 实现驱动像素LED显示屏 8*8点阵屏并演示滚动显示字符串

HDL · 发表于 2023-7-16 12:13:31

module rotate90( //8*8点阵旋转90度模块
input [63:0] in, //[64位宽] 8*8点阵数据
input lr, //旋转方向 0:向左旋转 1:向右旋转
output [63:0] out //[64位宽] 8*8点阵数据(旋转后的)
);
wire [63:0] j = in;
wire [63:0] l = {
j[7],j[15],j[23],j[31],j[39],j[47],j[55],j[63],
j[6],j[14],j[22],j[30],j[38],j[46],j[54],j[62],
j[5],j[13],j[21],j[29],j[37],j[45],j[53],j[61],
j[4],j[12],j[20],j[28],j[36],j[44],j[52],j[60],
j[3],j[11],j[19],j[27],j[35],j[43],j[51],j[59],
j[2],j[10],j[18],j[26],j[34],j[42],j[50],j[58],
j[1],j[9],j[17],j[25],j[33],j[41],j[49],j[57],
j[0],j[8],j[16],j[24],j[32],j[40],j[48],j[56]
};
wire [63:0] r = {
j[56],j[48],j[40],j[32],j[24],j[16],j[8],j[0],
j[57],j[49],j[41],j[33],j[25],j[17],j[9],j[1],
j[58],j[50],j[42],j[34],j[26],j[18],j[10],j[2],
j[59],j[51],j[43],j[35],j[27],j[19],j[11],j[3],
j[60],j[52],j[44],j[36],j[28],j[20],j[12],j[4],
j[61],j[53],j[45],j[37],j[29],j[21],j[13],j[5],
j[62],j[54],j[46],j[38],j[30],j[22],j[14],j[6],
j[63],j[55],j[47],j[39],j[31],j[23],j[15],j[7]
};
assign out = lr ? r : l;
endmodule
module ascii_8x8( //8*8点阵字符串字库模块
input [7:0] ascii, //[8位宽] ASCII码
output [63:0] data //[64位宽] 8*8点阵数据
);
reg [63:0] Q;
assign data = ascii[7] ? ~Q : Q;
always @(*) begin
case(ascii[6:0])
//7'h00:Q=64'h0000000000000000;
7'h01:Q=64'h3333CCCC3333CCCC;
7'h02:Q=64'h00183C7E18181818;
7'h03:Q=64'h00080CFEFE0C0800;
7'h04:Q=64'h30480C3E0C463F00;
7'h05:Q=64'h0000C07C6E6C6C00;
7'h06:Q=64'hFEFE000000000000;
7'h07:Q=64'h0707060606060606;
7'h08:Q=64'h1818181F1F000000;
7'h09:Q=64'h3399CC663399CC66;
7'h0A:Q=64'hCC993366CC993366;
7'h0B:Q=64'h000000FFFF000000;
7'h0C:Q=64'hC0C0C0C0C0C0C0C0;
7'h0D:Q=64'h000000003333CCCC;
7'h0E:Q=64'h1818181818181818;
7'h0F:Q=64'h181818F8F8181818;
7'h10:Q=64'h181818FFFF181818;
7'h11:Q=64'h181818F8F8000000;
7'h12:Q=64'h0000001F1F181818;
7'h13:Q=64'h000000000000FFFF;
7'h14:Q=64'h000000F8F8181818;
7'h15:Q=64'h181818FFFF000000;
7'h16:Q=64'h000000FFFF181818;
7'h17:Q=64'h1818181F1F181818;
7'h18:Q=64'h0F0F0F0F0F0F0F0F;
7'h19:Q=64'h00000000FFFFFFFF;
7'h1A:Q=64'h000000000F0F0F0F;
7'h1B:Q=64'h03030C0C03030C0C;
7'h1C:Q=64'hF0F0F0F000000000;
7'h1D:Q=64'h00000000F0F0F0F0;
7'h1E:Q=64'h0F0F0F0F00000000;
7'h1F:Q=64'h0F0F0F0FF0F0F0F0;
//7'h20:Q=64'h0000000000000000;
7'h21:Q=64'h1818181800001800;
7'h22:Q=64'h6666660000000000;
7'h23:Q=64'h6666FF66FF666600;
7'h24:Q=64'h187C063C603E1800;
7'h25:Q=64'h006630180C666200;
7'h26:Q=64'h3C663C1CE666FC00;
7'h27:Q=64'h6030180000000000;
7'h28:Q=64'h30180C0C0C183000;
7'h29:Q=64'h0C18303030180C00;
7'h2A:Q=64'h00663CFF3C660000;
7'h2B:Q=64'h0018187E18180000;
7'h2C:Q=64'h000000000018180C;
7'h2D:Q=64'h0000007E00000000;
7'h2E:Q=64'h0000000000181800;
7'h2F:Q=64'h00C06030180C0600;
7'h30:Q=64'h3C66766E66663C00;
7'h31:Q=64'h18181C1818187E00;
7'h32:Q=64'h3C6660300C067E00;
7'h33:Q=64'h3C66603860663C00;
7'h34:Q=64'h60707866FE606000;
7'h35:Q=64'h7E063E6060663C00;
7'h36:Q=64'h3C66063E66663C00;
7'h37:Q=64'h7E66301818181800;
7'h38:Q=64'h3C66663C66663C00;
7'h39:Q=64'h3C66667C60663C00;
7'h3A:Q=64'h0000180000180000;
7'h3B:Q=64'h000018000018180C;
7'h3C:Q=64'h70180C060C187000;
7'h3D:Q=64'h00007E007E000000;
7'h3E:Q=64'h0E18306030180E00;
7'h3F:Q=64'h3C66603018001800;
7'h40:Q=64'h3C66767606463C00;
7'h41:Q=64'h183C667E66666600;
7'h42:Q=64'h3E66663E66663E00;
7'h43:Q=64'h3C66060606663C00;
7'h44:Q=64'h1E36666666361E00;
7'h45:Q=64'h7E06061E06067E00;
7'h46:Q=64'h7E06061E06060600;
7'h47:Q=64'h3C66067666663C00;
7'h48:Q=64'h6666667E66666600;
7'h49:Q=64'h3C18181818183C00;
7'h4A:Q=64'h7830303030361C00;
7'h4B:Q=64'h66361E0E1E366600;
7'h4C:Q=64'h0606060606067E00;
7'h4D:Q=64'hC6EEFED6C6C6C600;
7'h4E:Q=64'h666E7E7E76666600;
7'h4F:Q=64'h3C66666666663C00;
7'h50:Q=64'h3E66663E06060600;
7'h51:Q=64'h3C666666663C7000;
7'h52:Q=64'h3E66663E1E366600;
7'h53:Q=64'h3C66063C60663C00;
7'h54:Q=64'h7E18181818181800;
7'h55:Q=64'h6666666666663C00;
7'h56:Q=64'h66666666663C1800;
7'h57:Q=64'hC6C6C6D6FEEEC600;
7'h58:Q=64'h66663C183C666600;
7'h59:Q=64'h6666663C18181800;
7'h5A:Q=64'h7E6030180C067E00;
7'h5B:Q=64'h3C0C0C0C0C0C3C00;
7'h5C:Q=64'h060C183060C00000;
7'h5D:Q=64'h3C30303030303C00;
7'h5E:Q=64'h00183C6600000000;
7'h5F:Q=64'h000000000000FE00;
7'h60:Q=64'h1818180000000000;
7'h61:Q=64'h00003C607C667C00;
7'h62:Q=64'h0006063E66663E00;
7'h63:Q=64'h00003C0606063C00;
7'h64:Q=64'h0060607C66667C00;
7'h65:Q=64'h00003C667E063C00;
7'h66:Q=64'h0070187C18181800;
7'h67:Q=64'h00007C66667C603E;
7'h68:Q=64'h0006063E66666600;
7'h69:Q=64'h0018001C18183C00;
7'h6A:Q=64'h006000606060603C;
7'h6B:Q=64'h000606361E366600;
7'h6C:Q=64'h001C181818183C00;
7'h6D:Q=64'h000066FEFED6C600;
7'h6E:Q=64'h00003E6666666600;
7'h6F:Q=64'h00003C6666663C00;
7'h70:Q=64'h00003E66663E0606;
7'h71:Q=64'h00007C66667C6060;
7'h72:Q=64'h00003E6606060600;
7'h73:Q=64'h00007C063C603E00;
7'h74:Q=64'h00187E1818187000;
7'h75:Q=64'h0000666666667C00;
7'h76:Q=64'h00006666663C1800;
7'h77:Q=64'h0000C6D6FE7C6C00;
7'h78:Q=64'h0000663C183C6600;
7'h79:Q=64'h00006666667C301E;
7'h7A:Q=64'h00007E30180C7E00;
7'h7B:Q=64'h380C180E180C3800;
7'h7C:Q=64'h1818180000181818;
7'h7D:Q=64'h1C30187018301C00;
7'h7E:Q=64'hCCFF330000000000;
//7'h7F:Q=64'h0000000000000000;
default:Q=64'h0000000000000000;
endcase
end
endmodule
module clk_div( //时钟分频模块输出频率=输入频率/分频系数/2
input clk, //时钟输入
input [15:0] div, //[16位宽]分配系数
output reg out //分频输出
);
initial out = 1'd0;
reg [15:0] i = 0;
always @(posedge clk) begin
i = i + 16'd1;
if(i >= div) begin
i = 0;
out <= !out;
end
end
endmodule
module led_array_8x8( //8*8点阵驱动模块
input clk,
input [63:0] display,
output fclk,
output reg [7:0] X,
output reg [7:0] Y
);
reg [2:0] i;
assign fclk = !i[2];
wire [63:0] j = ~display;
always @(posedge clk) begin
Y <= 8'd1<<i;
case(i)
3'd0:X <= j[63:56];
3'd1:X <= j[55:48];
3'd2:X <= j[47:40];
3'd3:X <= j[39:32];
3'd4:X <= j[31:24];
3'd5:X <= j[23:16];
3'd6:X <= j[15:8];
3'd7:X <= j[7:0];
endcase
i <= i + 3'd1;
end
endmodule
module string( //字符串模块
input clk,
output [7:0] ascii
);
reg [7:0] pc = 8'd0;
reg [7:0] Q = 8'd0;
assign ascii = Q;
always @(posedge clk) begin
case(pc)
8'd0:Q = "H";
8'd1:Q = "e";
8'd2:Q = "l";
8'd3:Q = "l";
8'd4:Q = "o";
8'd5:Q = " ";
8'd6:Q = "W";
8'd7:Q = "o";
8'd8:Q = "r";
8'd9:Q = "l";
8'd10:Q = "d";
8'd11:Q = "!";
8'd12:Q = " ";
8'd13:Q = "I";
8'd14:Q = "l";
8'd15:Q = "o";
8'd16:Q = "v";
8'd17:Q = "e";
8'd18:Q = "Y";
8'd19:Q = "o";
8'd20:Q = "u";
8'd21:Q = "!";
8'd22:Q = " ";
8'd23:Q = "0";
8'd24:Q = "1";
8'd25:Q = "2";
8'd26:Q = "3";
8'd27:Q = "4";
8'd28:Q = "5";
8'd29:Q = "6";
8'd30:Q = "7";
8'd31:Q = "8";
8'd32:Q = "9";
default:Q = 8'h00;
endcase
if(!Q) begin
pc <= 8'd0;
end else begin
pc <= pc + 8'd1;
end
end
endmodule
module roll( //8*8点阵滚动模块
input clk,
input [63:0] in,
output reg [63:0] out,
output sclk
);
reg [2:0] k = 3'd0;
reg [7:0] j = 8'd0;
wire [63:0] l = in;
assign sclk = !k[2];
initial out = 64'd0;
always @(posedge clk) begin
case(k)
3'd0:j <= l[63:56];
3'd1:j <= l[55:48];
3'd2:j <= l[47:40];
3'd3:j <= l[39:32];
3'd4:j <= l[31:24];
3'd5:j <= l[23:16];
3'd6:j <= l[15:8];
3'd7:j <= l[7:0];
endcase
k <= k + 3'd1;
out <= {out[55:0],j};
end
endmodule
/*
FPGA型号:EP2C5T144C8N 点阵屏型号:788BS
硬件连接: FPGA Pin <=> 点阵Pin
X[0]:Pin40 <=> Pin13
X[1]:Pin42 <=> Pin3
X[2]:Pin44 <=> Pin4
X[3]:Pin47 <=> Pin10
X[4]:Pin51 <=> Pin6
X[5]:Pin53 <=> Pin11
X[6]:Pin57 <=> Pin15
X[7]:Pin59 <=> Pin16
Y[0]:Pin41 <=> Pin9
Y[1]:Pin43 <=> Pin14
Y[2]:Pin45 <=> Pin8
Y[3]:Pin48 <=> Pin12
Y[4]:Pin52 <=> Pin1
Y[5]:Pin55 <=> Pin7
Y[6]:Pin58 <=> Pin2
Y[7]:Pin60 <=> Pin5
*/
module main(
input clk, //50Mhz有源晶振 Pin17
output [7:0] X, //[8位宽] 接8*8点阵X行
output [7:0] Y //[8位宽] 接8*8点阵Y列
);
wire clk_1Khz; //1Khz时钟
wire fclk; //上升沿完成一轮动态扫描
wire sclk; //上升沿读取下一个字母
wire rclk; //上升沿滚动显示一像素
wire [63:0] display;
wire [63:0] rotate;
wire [63:0] a8x8;
wire [63:0] l;
wire [7:0] ascii;
clk_div clk_div(
.clk(clk),
.div(16'd25000),
.out(clk_1Khz)
);
rotate90 rotate90_display(
.in(display),
.lr(1'b0),
.out(rotate)
);
led_array_8x8 led_array_8x8(
.clk(clk_1Khz),
.display(rotate),
.fclk(fclk),
.X(X),
.Y(Y)
);
clk_div clk_div2(
.clk(fclk),
.div(16'd4),
.out(rclk)
);
roll roll(
.clk(rclk),
.in(l),
.out(display),
.sclk(sclk)
);
string string(
.clk(sclk),
.ascii(ascii)
);
ascii_8x8 ascii_8x8(
.ascii(ascii),
.data(a8x8)
);
rotate90 rotate90_ascii(
.in(a8x8),
.lr(1'b1),
.out(l)
);
endmodule

复制代码

1心1亿 · 发表于 2023-7-19 09:17:15

来看看哈

222 · 发表于 2023-7-24 20:29:08

看看啥好东西

朵朵 · 发表于 2023-7-29 21:55:38

回来看看。

green · 发表于 2023-8-3 20:28:38

我也回复看看

吃货 · 发表于 2023-9-15 22:10:42

看看咋滚的

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Quartus Verilog HDL/FPGA 实现驱动 像素LED显示屏 8*8点阵屏 并演示滚动显示字符串

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Quartus Verilog HDL/FPGA 实现驱动像素LED显示屏 8*8点阵屏并演示滚动显示字符串