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- module hc266( //漏极开路的4组2输入 异或非门 同或门 VCC:Pin14 GND:Pin7
- //1组
- input A1, //输入A Pin1
- input B1, //输入B Pin2
- output Y1, //输出Y Pin3
- //2组
- input A2, //Pin5
- input B2, //Pin6
- output Y2, //Pin4
- //3组
- input A3, //Pin8
- input B3, //Pin9
- output Y3, //Pin10
- //4组
- input A4, //Pin12
- input B4, //Pin13
- output Y4 //Pin11
- );
- assign Y1 = (A1 ^ B1) ? 1'b0 : 1'bz;
- assign Y2 = (A2 ^ B2) ? 1'b0 : 1'bz;
- assign Y3 = (A3 ^ B3) ? 1'b0 : 1'bz;
- assign Y4 = (A4 ^ B4) ? 1'b0 : 1'bz;
- endmodule
- module main(
- input clk, //时钟输入
- output reg led //低电平(计算正确)点亮
- );
- wire [3:0] i;
- hc266 U1(
- .A1(1'b1),
- .B1(1'b0),
- .Y1(i[0]),
- .A2(1'b0),
- .B2(1'b1),
- .Y2(i[1]),
- .A3(1'b1),
- .B3(1'b0),
- .Y3(i[2]),
- .A4(1'b0),
- .B4(1'b1),
- .Y4(i[3])
- );
- always @(posedge clk) begin
- if(i == 4'd0) begin
- led <= 1'b0;
- end else begin
- led <= 1'b1;
- end
- end
- endmodule
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