Quartus Verilog HDL/FPGA 驱动两片级联74HC595与8位动态扫描数码管演示16进制的累加

HDL · 发表于 2022-2-2 08:33:23

module main(
input clk,
output reg SHCP,
output reg STCP,
output reg DS
);
parameter fosc = 50000000; //晶振频率
parameter hc595_num = 2; //595级联数量
parameter hc595_clkhz = 1000000; //595移位频率 1Mhz
parameter hc595_bit = hc595_num * 8;//595级联数*8 (位数)
reg [hc595_bit-1:0] hc595_dat; //修改该寄存器的值会实时发送到595
reg [hc595_bit-1:0] hc595_ram; //595数据缓存容器防止数据错乱
reg [31:0] hc595_i = 0; //595分频用
reg [31:0] hc595_bpc = 0; //595位指针
always @(posedge clk) begin //74HC595驱动
hc595_i = hc595_i + 1;
if(hc595_i >= fosc/hc595_clkhz/2) begin
hc595_i = 0;
SHCP = !SHCP;
if(SHCP) begin
if(hc595_bpc == 0) begin
hc595_ram = hc595_dat;
end
DS = hc595_ram[hc595_bit-hc595_bpc-1];
STCP = (hc595_bpc != hc595_bit-1);
hc595_bpc = hc595_bpc + 1;
if(hc595_bpc >= hc595_bit) begin
hc595_bpc = 0;
end
end
end
end
function [7:0] display; //16进制数码管段码查询
input [3:0] hex;
begin
case(hex)
4'h0:display = 8'h3F;
4'h1:display = 8'h06;
4'h2:display = 8'h5B;
4'h3:display = 8'h4F;
4'h4:display = 8'h66;
4'h5:display = 8'h6D;
4'h6:display = 8'h7D;
4'h7:display = 8'h07;
4'h8:display = 8'h7F;
4'h9:display = 8'h6F;
4'hA:display = 8'h77;
4'hB:display = 8'h7C;
4'hC:display = 8'h39;
4'hD:display = 8'h5E;
4'hE:display = 8'h79;
4'hF:display = 8'h71;
endcase
end
endfunction
parameter seg_hz = 10000; //数码管扫描频率 10Khz
reg [31:0] seg_i = 0;
reg [2:0] seg_j = 0;
reg [7:0] seg_k;
reg [31:0] seg_l;
reg [31:0] seg_hex = 0; //修改该寄存器的值会实时显示到数码管
always @(posedge clk) begin //数码管动态扫描
seg_i = seg_i + 1;
if(seg_i >= fosc/seg_hz) begin
seg_i = 0;
seg_j <= seg_j + 1'b1;
if(seg_j == 0) begin
seg_l = seg_hex;
end
case(seg_j)
0:seg_k=display(seg_l[31:28]);
1:seg_k=display(seg_l[27:24]);
2:seg_k=display(seg_l[23:20]);
3:seg_k=display(seg_l[19:16]);
4:seg_k=display(seg_l[15:12]);
5:seg_k=display(seg_l[11:8]);
6:seg_k=display(seg_l[7:4]);
7:seg_k=display(seg_l[3:0]);
default:seg_k=0;
endcase
//共阴或共阳如果显示不正确请修改以下两行代码
hc595_dat[15:8] = seg_k; //位码
hc595_dat[7:0] = ~(1'b1 << seg_j); //段码
end
end
reg [31:0] tmp_m = 0;
always @(posedge clk) begin //数码管值 1毫秒+1
tmp_m = tmp_m + 1'b1;
if(tmp_m >= fosc/1000) begin
tmp_m = 0;
seg_hex = seg_hex + 1'b1;
end
end
endmodule

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Quartus Verilog HDL/FPGA 驱动两片级联74HC595与8位动态扫描数码管 演示16进制的累加

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Quartus Verilog HDL/FPGA 驱动两片级联74HC595与8位动态扫描数码管演示16进制的累加