Quartus Verilog HDL/FPGA 驱动3片级联74HC595的3位静态共阴数码管并演示000~999 累加

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HDL

发表于 2022-8-18 19:32:01 | 显示全部楼层 |阅读模式

module main(
input clk, //50Mhz Pin17
output reg SHCP, //74HC595 Pin30
output reg STCP, //74HC595 Pin31
output reg DS //74HC595 Pin32
);
parameter fosc = 50000000; //晶振频率
parameter hc595_num = 3; //595级联数量
parameter hc595_clkhz = 1000000; //595移位频率 1Mhz
parameter hc595_bit = hc595_num * 8;//595级联数*8 (位数)
reg [hc595_bit-1:0] hc595_dat; //修改该寄存器的值会实时发送到595
reg [hc595_bit-1:0] hc595_ram; //595数据缓存容器防止数据错乱
reg [31:0] hc595_i = 0; //595分频用
reg [31:0] hc595_bpc = 0; //595位指针
function [7:0] display; //16进制数码管段码查询
input [3:0] hex;
begin
case(hex)
4'h0:display = 8'h3F;
4'h1:display = 8'h06;
4'h2:display = 8'h5B;
4'h3:display = 8'h4F;
4'h4:display = 8'h66;
4'h5:display = 8'h6D;
4'h6:display = 8'h7D;
4'h7:display = 8'h07;
4'h8:display = 8'h7F;
4'h9:display = 8'h6F;
4'hA:display = 8'h77;
4'hB:display = 8'h7C;
4'hC:display = 8'h39;
4'hD:display = 8'h5E;
4'hE:display = 8'h79;
4'hF:display = 8'h71;
endcase
end
endfunction
reg [9:0] nbr; //数码管正在显示的数字 0~999
always @(posedge clk) begin
hc595_dat[23:16] <= display(nbr % 10); //74HC595:U3
hc595_dat[15:8] <= display((nbr)/ 10 %10); //74HC595:U2
hc595_dat[7:0] <= display((nbr/100) %10); //74HC595:U1
end
reg [31:0] i;
always @(posedge clk) begin
i = i + 1'b1;
if(i >= fosc/10) begin
i = 0;
nbr = nbr + 1'b1;
if(nbr > 999) begin
nbr = 0;
end
end
end
always @(posedge clk) begin //74HC595驱动
hc595_i = hc595_i + 1;
if(hc595_i >= fosc/hc595_clkhz/2) begin
hc595_i = 0;
SHCP = !SHCP;
if(SHCP) begin
if(hc595_bpc == 0) begin
hc595_ram = hc595_dat;
end
DS = hc595_ram[hc595_bit-hc595_bpc-1];
STCP = (hc595_bpc != hc595_bit-1);
hc595_bpc = hc595_bpc + 1;
if(hc595_bpc >= hc595_bit) begin
hc595_bpc = 0;
end
end
end
end
endmodule

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Quartus, Verilog, FPGA, 74HC595, 数码管

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Quartus Verilog HDL/FPGA 驱动3片级联74HC595的3位静态共阴数码管并演示000~999 累加

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