Quartus Verilog HDL/FPGA 驱动2片级联74HC595的4位动态扫描共阳数码管演示0~9999累加

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HDL

发表于 2022-9-23 15:52:36 | 显示全部楼层 |阅读模式

module main(
input clk, //50Mhz Pin17
output reg SHCP, //74HC595 Pin30 上升沿将DS数据移入内锁存器
output reg STCP, //74HC595 Pin31 上升沿将内锁存器的数据转移到外锁存器
output reg DS //74HC595 Pin32 移位频率:主时钟的1/4 (12.5Mhz)
);
reg [1:0] i;
parameter hc595_num = 2; //595级联数量:级联几片74HC595 这里就改成几
parameter hc595_bit = hc595_num * 8 - 1; //595位数:级联数量*8-1 (请勿修改)
integer BitPC = 0; //595位指针范围:0~595位数
reg [0:hc595_bit] hc595_ram; //595数据缓存容器防止数据错乱 (从低到高位发送)
reg [hc595_bit:0] hc595_dat; //该寄存器的值被改变将实时传送到595
always @(posedge clk) begin //74HC595驱动
SHCP <= ^i;
STCP <= ^(i - 2'b1) & !BitPC;
if(!i) begin
if(!BitPC) begin
hc595_ram = hc595_dat;
end
DS <= hc595_ram[BitPC];
BitPC = BitPC + 1;
if(BitPC > hc595_bit) begin
BitPC = 0;
end
end
i <= i + 2'b1;
end
reg [13:0] nbr = 0; //数码管正在显示的数字 0~9999
function [7:0] display; //16进制共阴数码管段码查询
input [3:0] hex;
begin
case(hex)
4'h0:display = 8'h3F;
4'h1:display = 8'h06;
4'h2:display = 8'h5B;
4'h3:display = 8'h4F;
4'h4:display = 8'h66;
4'h5:display = 8'h6D;
4'h6:display = 8'h7D;
4'h7:display = 8'h07;
4'h8:display = 8'h7F;
4'h9:display = 8'h6F;
4'hA:display = 8'h77;
4'hB:display = 8'h7C;
4'hC:display = 8'h39;
4'hD:display = 8'h5E;
4'hE:display = 8'h79;
4'hF:display = 8'h71;
endcase
end
endfunction
reg [1:0] j = 0;
always @(negedge STCP) begin //数码管动态扫描
case(j)
2'd0:hc595_dat[15:8] <= ~display(nbr % 10);
2'd1:hc595_dat[15:8] <= ~display((nbr) / 10 %10);
2'd2:hc595_dat[15:8] <= ~display((nbr) / 100 %10);
2'd3:hc595_dat[15:8] <= ~display((nbr) / 1000 %10);
endcase
hc595_dat[7:4] <= 4'b0;
hc595_dat[3:0] <= (4'b1 << j);
j <= j + 2'b1;
end
integer k = 0;
always @(posedge clk) begin //数字0~9999累加
k = k + 1;
if(k >= 5000000) begin
k = 0;
nbr = nbr + 1'b1;
if(nbr > 9999) begin
nbr = 0;
end
end
end
endmodule

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Quartus, Verilog, FPGA, 74HC595, 数码管

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Quartus Verilog HDL/FPGA 驱动2片级联74HC595的4位动态扫描共阳数码管演示0~9999累加

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