Quartus Verilog HDL/FPGA 实现硬件CRC32算法模块板的功能测试验证程序 (带LED指示灯)

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HDL

发表于 2023-1-25 20:53:41 | 显示全部楼层 |阅读模式

本帖最后由 HDL 于 2023-1-25 20:53 编辑

硬件CRC32算法原理图:
https://www.fedcba9876543210.com/thread-4036-1-1.html

module crc32_table( //CRC32查表模块
input [7:0] in, //8位宽地址
output [31:0] out //32位宽值
);
reg [31:0] crc;
always @(*) begin
crc = {24'd0,in};
repeat(8) begin
crc = (crc >> 1) ^ (crc & 1 ? 32'hEDB88320 : 0);
end
end
assign out = crc;
endmodule
module crc32_byte( //CRC32 字节计算模块
input [31:0] in_crc32, //输入CRC32
input [7:0] dat, //字节值
output [31:0] out_crc32 //输出CRC32
);
wire [31:0] out;
crc32_table crc32_table(
.in(in_crc32[7:0] ^ dat),
.out(out)
);
assign out_crc32 = out ^ (in_crc32 >> 8);
endmodule
/*
CRC32算法板:由18个74HC86(71个异或门)组成(组合逻辑) 或另一颗FPGA/CPLD芯片
如果全部计算正确，则在LED闪烁 2^40/12500000=87960.930222 秒后转为常亮
*/
module main(
input [31:0] out_crc32, //接CRC32算法板输出 32个Pin
output [31:0] in_crc32, //接CRC32算法板输入 32个Pin
output [7:0] dat, //接CRC32算法板字节输入 B0~B7 8个Pin
input clk, //50Mhz有源晶振时钟 Pin17
input rst, //复位按钮 (低电平按下) Pin144
output reg led //LED Pin3 计算中:闪烁错误:熄灭正确:常亮 (低电平点亮)
);
wire [31:0] out_crc32B;
reg [31:0] in_crc32B;
reg [7:0] datB;
assign in_crc32 = in_crc32B;
assign dat = datB;
crc32_byte crc32_byte( //模块实例化
.in_crc32(in_crc32),
.dat(dat),
.out_crc32(out_crc32B)
);
//时钟分频
reg [1:0] i;
always @(posedge clk) begin
i <= i + 2'd1;
end
reg err;
reg ok;
reg [22:0] j;
initial err = 1'd0;
initial ok = 1'd0;
always @(posedge i[1]) begin //12.5Mhz
if(!rst) begin
led <= 1'd1;
err = 1'd0;
ok = 1'd0;
{in_crc32B,datB} = 40'd0;
j = 23'd0;
end else begin
if(err) begin
led <= 1'd1;
end else begin
if(ok) begin
led <= 1'd0;
end else begin
{datB,in_crc32B} = {datB,in_crc32B} + 40'd1;
j = j + 23'd1;
if(j >= 23'd1562500) begin
j = 23'd0;
led <= !led;
end
if(out_crc32 != out_crc32B) begin
err <= 1'd1;
end else if(!{datB,in_crc32B}) begin
ok <= 1'd1;
end
end
end
end
end
endmodule

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Quartus, Verilog, HDL, FPGA, CRC32

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Quartus Verilog HDL/FPGA 实现硬件CRC32算法模块板的功能测试验证程序 (带LED指示灯)

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